存储器子系统的组成与接口.docx

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1、6Ll9/9/6007附录10：英文原文MemorySubsystemOrganizationandInterfacingInthissectionweexaminetheconstructionandfunctionsofthememorysubsystemofacomputer.Wereviewthedifferenttypesofphysicalmemoryandtheinternalorganizationoftheirchips.Wediscusstheconstructionofthememorysubsystem,aswellasmultibytewordorganization

2、sandadvancedmemoryorganizations.1 TypesofMemoryTherearetwotypesofmemorychips;readonlymemory(ROM)andrandomaccessmemory(RAM).ReadOnlyMemory(ROM)chipsaredesignedforapplicationsinwhichdataisonlyread.(Thisdatacanincludeprograminstructions.)Thesechipsareprogrammedwithdatabyanexternalprogrammingunitbeforet

3、heyareaddedtothecomputersystem.Oncethisisdone,thedatausuallydoesnotchange.AROMchipalwaysretainsitsdata,evenwhenpowertothechipisturnedoff.Asanexample,anembeddedcontrollerforamicrowaveovenmightcontinuouslyrunoneprogramthatdoesnotchange.ThatprogramwouldbestoredinaROM.RandomAccessMemory(RAM),alsocalledr

4、ead/writememory,canbeusedtostoredatathatchange.ThisisthetypeofmemoryreferredtoasXMBofmemoryinadsforPCs.UnlikeROM,RAMchipslosetheirdataoncepowerisshutoff.Manycomputersystem,includingpersonalcomputers,includebothROMandRAM.2 InternalChipOrganizationTheinternalorganizationsofROMandRAMchipsaresimilar.Toi

5、llustratethesimplestorganization,alinearorganization,consideran8x2ROMchip.Forsimplicity,programmingcomponentsarenotshownoThischiphasthreeaddressinputsandtwodataoutputs,and16bitsofinternalstoragearrangedaseight2-bitlocations.Thethreeaddressbitsaredecodedtoselectoneoftheeightlocations,butonlyifthechip

6、enableisactive.IfCE=O,thedecoderiddisabledandnolocationisselected.Thetri-statebuffersforthatlocationscellsareenabled,allowingdatatopasstotheoutputbuffers.IfbothCEandOEsetto1,thesebuffersareenabledandthedataisoutputfromthechip;otherwisetheoutputsaretri-stated.Asthenumberofthelocationsincreases,thesiz

7、eoftheaddressdecoderneededinalinearorganizationbecomesprohibitivelylarge.Toremedythisproblem,thememorychipcanbedesignedusingmultipledimensionsofdecoding.Inlargememorychips,thissavingscanbesignificant.Considera4096xlchip.Thelinearorganizationwillrequirea12to4096decoder,thesizeofwhichisproportionaltot

8、henumberofoutputs.(Thesizeofannto2ndecoderidthussaidtobeO(2n).)Ifthechipisorganizedasa64x64twodimensionalarrayinstead,itwillhavetwo6to64decoders:onetoselectoneofthe64rowsandtheothertoselectoneofthe64cellswithintherow.Thesizeofthedecodersisproportionalto2x64,orO(2x2l72)=O(2l72+1).Forthischip,thetwode

9、coderstogetherareabout3percentofthesizeoftheonelargedecoder.3 MemorySubsystemConfigurationItisveryeasytosetupamemorysystemthatconsistsofasinglechip.Wesimpleyconnecttheaddress,data,andcontrolsignalsfromtheirsystembusesandthejobisdone.However,mostmemorysystemsrequiremorethanonechip.Followingaresomemet

10、hodsforcombiningmemorychipstoformamemorysubsystem.Twoormorechipscanbecombinedtocreatememorywithmorebitsperlocation.Thisisdonebyconnectingthecorrespondingaddressandcontrolsignalsofthechips,andconnectingtheirdatapinstodifferentbitsofthedatabus.Forexample,two8x2chipscanbecombinedtocreatean8x4memory,ass

11、howninFigure2-4.Bothchipsreceivethesamethreeaddressinputsfromthebus,aswellasthesamechipenableandoutputenablesignals.(Fornowitisonlyimportanttoknowthatthesignalsarethesameforbothchips;weshowthelogictogeneratethesesignalsshortly.)Thedatapinsofthefirstchipareconnectedtobits3and2ofthedatabus,andthoseoft

12、heotherchipareconnectedtobits1and0.D3D2D3D2Figure4An8x4memorysubsystemconstructedfromtwo8x2ROMChipsWhentheCPUreadsdata,itplacestheaddressontheaddressbus.BothchipsreadinaddressbitsA2,Al,andAoandperfonntheirinternaldecoding.IftheCEandOEsignalsareactivated,thechipsoutputtheirdataontothefombitsofthedata

13、bus.Sincetheaddressandenablesignalsarethesameforbothchips,eitherbothchipsorneitherchipisactiveatanygiventime.Thecomputerneverhasonlyoneofthetwoactive.Forthisreason,theyactjustasasingle8x4chip,atleastasfarastheCPUisconcerned.Insteadofcreatingwiderwords,chipscanbecombinedtocreatemorewords.Thesametwo8x

14、2chipscouldinsteadbeconfiguredasa16x2memorysubsystem.ThisisillustratedinFigure2-5（八）.Theupperchipisconfiguredas,memorylocationsOto7(0000toOIII)andthelowerchipaslocations8to15(100Oto11II).TheupperchipalwayshasA3=OandthelowerchiphasA3=I.Thisdifferenceisusedtoselectoneofthetwochips.WhenA3=0,theupperchi

15、pisenabledandthelowerchipisdisabled;whenA3=1,theoppositeoccurs.(Asshowninthefigure9otherconditionsmustalsooccurorneitherchipwillbeselected.)Theoutputenablescanbeconnected,sinceonlythechipthatisenabledwilloutputdata.Sincebothchipscorrespondtothesamedatabits,bothareconnectedtoDIandDoofthedatabus.Thisc

16、onfigurationuseshigh-orderinterleaving.Allmemorylocationswithinachiparecontiguouswithinsystemmemory.However,thisdoesnothavetobethecase.ConsidertheconfigurationshowninFigure2-5(b),whichuseslow-orderinterleaving.TheupperchipisenabledwhenAO=OorbyaddressesXXXO,inthiscase0,2,4,6,8,10,12,and14.Thelowerchipisenabledwhen.A0=l,whichistrueforaddresses1,3,5,7,9,11,13and15.BothlookthesametotheCPU,butlow-orderinterleavingcanoffersomespeedadvantagesf