存储器子系统的组成与接口.docx

6Ll9/9/6007附录10：英文原文MemorySubsystemOrganizationandInterfacingInthissectionweexaminetheconstructionandfunctionsofthememorysubsystemofacomputer.Wereviewthedifferenttypesofphysicalmemoryandtheinternalorganizationoftheirchips.Wediscusstheconstructionofthememorysubsystem,aswellasmultibytewordorganizationsandadvancedmemoryorganizations.1 TypesofMemoryTherearetwotypesofmemorychips;readonlymemory(ROM)andrandomaccessmemory(RAM).ReadOnlyMemory(ROM)chipsaredesignedforapplicationsinwhichdataisonlyread.(Thisdatacanincludeprograminstructions.)Thesechipsareprogrammedwithdatabyanexternalprogrammingunitbeforetheyareaddedtothecomputersystem.Oncethisisdone,thedatausuallydoesnotchange.AROMchipalwaysretainsitsdata,evenwhenpowertothechipisturnedoff.Asanexample,anembeddedcontrollerforamicrowaveovenmightcontinuouslyrunoneprogramthatdoesnotchange.ThatprogramwouldbestoredinaROM.RandomAccessMemory(RAM),alsocalledread/writememory,canbeusedtostoredatathatchange.ThisisthetypeofmemoryreferredtoasXMBofmemoryinadsforPCs.UnlikeROM,RAMchipslosetheirdataoncepowerisshutoff.Manycomputersystem,includingpersonalcomputers,includebothROMandRAM.2 InternalChipOrganizationTheinternalorganizationsofROMandRAMchipsaresimilar.Toillustratethesimplestorganization,alinearorganization,consideran8x2ROMchip.Forsimplicity,programmingcomponentsarenotshownoThischiphasthreeaddressinputsandtwodataoutputs,and16bitsofinternalstoragearrangedaseight2-bitlocations.Thethreeaddressbitsaredecodedtoselectoneoftheeightlocations,butonlyifthechipenableisactive.IfCE=O,thedecoderiddisabledandnolocationisselected.Thetri-statebuffersforthatlocation'scellsareenabled,allowingdatatopasstotheoutputbuffers.IfbothCEandOEsetto1,thesebuffersareenabledandthedataisoutputfromthechip;otherwisetheoutputsaretri-stated.Asthenumberofthelocationsincreases,thesizeoftheaddressdecoderneededinalinearorganizationbecomesprohibitivelylarge.Toremedythisproblem,thememorychipcanbedesignedusingmultipledimensionsofdecoding.Inlargememorychips,thissavingscanbesignificant.Considera4096xlchip.Thelinearorganizationwillrequirea12to4096decoder,thesizeofwhichisproportionaltothenumberofoutputs.(Thesizeofannto2ndecoderidthussaidtobeO(2n).)Ifthechipisorganizedasa64x64twodimensionalarrayinstead,itwillhavetwo6to64decoders:onetoselectoneofthe64rowsandtheothertoselectoneofthe64cellswithintherow.Thesizeofthedecodersisproportionalto2x64,orO(2x2l72)=O(2l72+1).Forthischip,thetwodecoderstogetherareabout3percentofthesizeoftheonelargedecoder.3 MemorySubsystemConfigurationItisveryeasytosetupamemorysystemthatconsistsofasinglechip.Wesimpleyconnecttheaddress,data,andcontrolsignalsfromtheirsystembusesandthejobisdone.However,mostmemorysystemsrequiremorethanonechip.Followingaresomemethodsforcombiningmemorychipstoformamemorysubsystem.Twoormorechipscanbecombinedtocreatememorywithmorebitsperlocation.Thisisdonebyconnectingthecorrespondingaddressandcontrolsignalsofthechips,andconnectingtheirdatapinstodifferentbitsofthedatabus.Forexample,two8x2chipscanbecombinedtocreatean8x4memory,asshowninFigure2-4.Bothchipsreceivethesamethreeaddressinputsfromthebus,aswellasthesamechipenableandoutputenablesignals.(Fornowitisonlyimportanttoknowthatthesignalsarethesameforbothchips;weshowthelogictogeneratethesesignalsshortly.)Thedatapinsofthefirstchipareconnectedtobits3and2ofthedatabus,andthoseoftheotherchipareconnectedtobits1and0.D3D2D3D2Figure4An8x4memorysubsystemconstructedfromtwo8x2ROMChipsWhentheCPUreadsdata,itplacestheaddressontheaddressbus.BothchipsreadinaddressbitsA2,Al,andAoandperfonntheirinternaldecoding.IftheCEandOEsignalsareactivated,thechipsoutputtheirdataontothefombitsofthedatabus.Sincetheaddressandenablesignalsarethesameforbothchips,eitherbothchipsorneitherchipisactiveatanygiventime.Thecomputerneverhasonlyoneofthetwoactive.Forthisreason,theyactjustasasingle8x4chip,atleastasfarastheCPUisconcerned.Insteadofcreatingwiderwords,chipscanbecombinedtocreatemorewords.Thesametwo8x2chipscouldinsteadbeconfiguredasa16x2memorysubsystem.ThisisillustratedinFigure2-5（八）.Theupperchipisconfiguredas,memorylocationsOto7(0000toOIII)andthelowerchipaslocations8to15(100Oto11II).TheupperchipalwayshasA3=OandthelowerchiphasA3=I.Thisdifferenceisusedtoselectoneofthetwochips.WhenA3=0,theupperchipisenabledandthelowerchipisdisabled;whenA3=1,theoppositeoccurs.(Asshowninthefigure9otherconditionsmustalsooccurorneitherchipwillbeselected.)Theoutputenablescanbeconnected,sinceonlythechipthatisenabledwilloutputdata.Sincebothchipscorrespondtothesamedatabits,bothareconnectedtoDIandDoofthedatabus.Thisconfigurationuseshigh-orderinterleaving.Allmemorylocationswithinachiparecontiguouswithinsystemmemory.However,thisdoesnothavetobethecase.ConsidertheconfigurationshowninFigure2-5(b),whichuseslow-orderinterleaving.TheupperchipisenabledwhenAO=OorbyaddressesXXXO,inthiscase0,2,4,6,8,10,12,and14.Thelowerchipisenabledwhen.A0=l,whichistrueforaddresses1,3,5,7,9,11,13and15.BothlookthesametotheCPU,butlow-orderinterleavingcanoffersomespeedadvantagesf