盛群单片机简介.ppt
2023/4/2Introduction of Holtek HT-46series MCU2023/4/2ContentFamily of A/D Type MCUi.Cost-Effective A/D type MCUii.A/D type MCUiii.A/D with LCD type MCUiv.A/D with VFD type MCUDetail of HT46R24i.Features of HT46R24ii.Block Diagramiii.Function Description(ROM, RAM, Interrupt, I/O, Timer, Buzzer, Oscillator, ADC, I2C, PWM, .)2023/4/2Cost-Effective A/D Type MCU2023/4/2A/D Type MCU2023/4/2A/D with LCD Type MCU2023/4/2Features of HT46R242023/4/2Block Diagram2023/4/2HT46X24 PIN ASSIGMENT2023/4/2Program ROM and Interrupt Vector2023/4/2RAM MAPPINGSpecial Purpose Data Memory General Purpose Data Memory 00h IAR0 10h TMR1L 20h HADR 01h MP0 11h TMR1C 21h HCR 02h IAR1 12h PA 22h HSR 03h MP1 13h PAC 23h HDR 04h BP 14h PB 24h ADRL 05h ACC 15h PBC 25h ADRH 06h PCL 16h PC 26h ADCR 07h TBLP 17h PCC 27h ACSR 08h TBLH 18h PD 28h PF 09h N.A. 19h PDC 29h PFC 0ah STATUS 1ah PWM0 0bh INTC0 1bh PWM1 0ch TMR0H 1ch PWM2 0dh TMR0L 1dh PWM3 0eh TMR0C 1eh INTC1 0fh TMR1H 1fh N.A. 2ah . . . . 3fh N.A. 40h . . . . . . . . . . . . . . . ffh BANK 0 40h . . . . . . . . . . . . . . . ffh BANK 1 2023/4/263 InstructionsArithmeticlADD, SUBIncrement & DecrementlINC, INCA, DECLogic OperationlAND, OR, XORRotatelRR, RRC, RLData MovelMOVBit operationlSET, CLRTable ReadlTABRDC, TABRDLBranchlJMP, SZ, RET, RETIMiscellaneouslNOP, SWAP, HALT2023/4/2Arithmetic 2023/4/2Logic 2023/4/2Increment, Decrement, Rotate, Data Move, Bit Operation 2023/4/2Branch 2023/4/2Table Read ,Miscellaneous 2023/4/2Indirect AddressingIndirect addressing Register:lIRA0,IRA1.Memory Pointers:lMP0,MP1.2023/4/2Status Register2023/4/2I/O Structure 2023/4/2InterruptInterrupt has priority issue.Once an interrupt subroutine is serviced, all the other interrupts will be block ( by cleaning the EMI flag).After the subroutine set the “RETI”, the EMI will be set again.2023/4/2Interrupt control register2023/4/2Interrupt Scheme2023/4/2Timer/Event Counter 02023/4/2Timer/Event Counter 12023/4/2Timer Control Register 02023/4/2Timer Control Register 12023/4/23 modes available for the Timer/Counter 1.Timer Mode 2.Event Counter Mode 3.Pulse Width Mode 2023/4/24 steps to setup in the Timer Mode 1.Set to Timer Mode by writing 10 to TM1, TM0 2.Set the initial timer TMR value 3.Enable the corresponding interrupt by setting the ETI and EMI bit 4.Start the Timer by setting the TON bit of the TMRC 2023/4/25 steps to setup in the Even Counter Mode 1.Set to Event Counter Mode by writing 01 to TM1, TM0 2.Select TE=1 to count on the falling edge or TE=0 to count on the rising edge 3.Set the Timer initial value into TMR 4.Enable the corresponding interrupt by setting the ETI and EMI bits 5.Start the Timer by setting the TON bit in the TMRC register2023/4/25 steps to setup in the Pulse Width Measurement Mode 1.Set to Pulse Width Mode by writing 11 to TM1, TM0 2.Select TE=1 to measure a High Pulse Width and TE=0 to measure a Low Pulse Width 3.Set the Timer initial value, TMR, usually set to 0H for Pulse Width Measurements 4.Enable the corresponding interrupt by setting the ETI and EMI bits 5.Start the Timer by setting the TON bit in the TMRC 2023/4/2Programmable Frequency Divider (PFD) and BuzzerPFD is pin shared with PA3(selected via configuration optional).Clock source of PFD is come from timer0 or timer1 overflow signal (selected via configuration optional).PFD output is controlled by switch on/off PA3.2023/4/2Watchdog TimerThe watchdog timer is provided to prevent program uncontrollable .3 clock sources can be selected as watchdog timing source: (by configuration)lT1(fsys /4) ,32KHz RTC,WDT OSC output.lAt HALT, only WDT OSC or RTC oscillator is still running.2023/4/2Watchdog RegisterIf watchdog timeout ,the system will be reset. The status bit “TO” will be set.There are two method of using software to clear watchdog timer (selected by configuration) :lOne instruction : CLR WDTlTwo instruction : CLR WDT1, CLR WDT2 2023/4/2PWMPWM is Pulse Width Modulator. There are two modes 6+2 or 7+1 selected by configuration.User can change the duty cycle by softwarelby writing data to PWM0PWM3 special data register.PWM function can be controlled On/Off by software.lEnable PWM output : SET PD0lDisable PWM output : CLR PD0 2023/4/2PWM 6+2 Mode2023/4/2PWM 7+1 Mode2023/4/2Analog to Digital ConverterThe HT46R24 has a 10-bit ADC. ADC can be disabled by software.Max. 4 or 8 channels can input to the ADC.lChannels set in ADCR by softwareADC channels are pin-shared with Port B.lAs ADC input or Port B set in ADCR by softwareInput range is from 0 to VDD.Min. ADC clock period is 1 us.ADC sampling time is 32 ADC clocks.ADC convert time is 76 ADC clocks.Max. INL 1 LSB.2023/4/2ADC Convert Data RegisterADRL/ADRH are two registers to store the ADC convert data.2023/4/2A/D Convert Control Register2023/4/2A/D Convert Clock Source Register2023/4/2A/D Convert Timing Diagram2023/4/2I2C Bus InterfaceI2C bus is a bidirectional 2-wire serial interface.lSCL : serial clock pin.lSDA : serial data pin.I2C output is of open drain . An external pull high
